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- research-articleSeptember 2021
MSYNC: A Generalized Formal Design Pattern for Virtually Synchronous Multirate Cyber-physical Systems
ACM Transactions on Embedded Computing Systems (TECS), Volume 20, Issue 5sArticle No.: 105, Pages 1–26https://doi.org/10.1145/3477036TTA and PALS are two prominent formal design patterns—with different strengths and weaknesses—for virtually synchronous distributed cyber-physical systems (CPSs). They greatly simplify the design and verification of such systems by allowing us to design ...
- research-articleApril 2016
SMT-Based Analysis of Virtually Synchronous Distributed Hybrid Systems
HSCC '16: Proceedings of the 19th International Conference on Hybrid Systems: Computation and ControlPages 145–154https://doi.org/10.1145/2883817.2883849This paper presents general techniques for verifying virtually synchronous distributed control systems with interconnected physical environments. Such cyber-physical systems (CPSs) are notoriously hard to verify, due to their combination of nontrivial ...
- short-paperMay 2015
Voltage-Boosted Synchronizers
GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSIPages 307–312https://doi.org/10.1145/2742060.2742075With a specified Mean Timing Between Failure (MTBF), the metastability resolution time of synchronizers possibly constrains the system performance. To enhance metastability resolution time under single low-voltage supply environments, Voltage-Boosted ...
- ArticleJune 2008
Distributed Algorithms to Form Cluster Based Spanning Trees in Wireless Sensor Networks
ICCS '08: Proceedings of the 8th international conference on Computational Science, Part IPages 519–528https://doi.org/10.1007/978-3-540-69384-0_57We propose two algorithms to form spanning trees in sensor networks. The first algorithm forms hierarchical clusters of spanning trees with a given root, the sink . All of the nodes in the sensor network are then classified iteratively as subroot , ...
- articleJanuary 2006
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS) (ENTCS), Volume 146, Issue 2Pages 5–28https://doi.org/10.1016/j.entcs.2005.05.033This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insensitive systems by Singh and Theobald [Montek Singh and Michael Theobald. ...
- articleDecember 2004
Scan Test Strategy for Asynchronous-Synchronous Interfaces
Journal of Electronic Testing: Theory and Applications (JELT), Volume 20, Issue 6Pages 639–645https://doi.org/10.1007/s10677-004-4251-3In the coming years, the well-known synchronous design style will not be able to keep pace with the increase speed and capabilities of integration of advanced processes. New design paradigms, like core reuse of the already designed synchronous modules ...
- research-articleOctober 2000
Phase Clocks for Transient Fault Repair
IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume 11, Issue 10Pages 1048–1057https://doi.org/10.1109/71.888644Phase clocks are synchronization tools that implement a form of logical time in distributed systems. For systems tolerating transient faults by self-repair of damaged data, phase clocks can enable reasoning about the progress of distributed repair ...
- ArticleAugust 1998
Coordination of Active Objects by means of Explicit Connections
DEXA '98: Proceedings of the 9th International Workshop on Database and Expert Systems ApplicationsPage 572Although coordination of multiple activities is a fundamental goal of object-oriented concurrent programming languages, there is only limited support for its specification and abstraction at the language level. This leads to a mismatch between ...
- research-articleJuly 1992
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
IEEE Transactions on Computers (ITCO), Volume 41, Issue 7Pages 858–872https://doi.org/10.1109/12.256454Continuous advances in VLSI technology have made it possible to implement a system on a chip. One consequence of this is that the system will use a homogeneous technology for interconnections, gates, and synchronizers. Another consequence is that the ...