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FPGAs are programmable devices that are interesting for streaming-style applications. Using vendor-independent programming models such as OpenCL for FPGAs can aid the development effort and prevent vendor lock-in. OpenCL pipes included in the OpenCL ...

Hybrid dataflow/von Neumann processors expose their processing units and datapaths to the compiler to exploit the instruction-level parallelism of sequential programs. Generating code from dataflow graphs for such processors that use FIFO-buffered ...

In the dataflow computation model, tasks are executed according to data dependencies, instead of following program order, enabling natural parallelism exploitation. Sucuri is a dataflow library for Python that allows transparent execution of applications ...

This paper presents DARSA, a Dataflow Application Resource and Sub-graph Analysis tool. DARSA can be used for early and accurate results for design space exploration of dataflow applications. Additionally DARSA can be used to extrapolate Coarse-Grain ...

Dataflow computing is proved to be promising in high-performance computing. However, traditional dataflow architectures are general-purpose and not efficient enough when dealing with typical scientific applications due to low utilization of function ...

This paper presents CSense - a stream-processing toolkit for developing robust and high-rate mobile sensing application in Java. CSense addresses the needs of these systems by providing a new programming model that supports flexible application ...

Many-core processors provide the raw computation power required by modern high-performance multimedia and signal processing workloads. The translation of this into execution performance is often constrained by the overheads of communication between ...

Multidisciplinary dataflow computing is a powerful approach to scientific computing that has led to orders-of-magnitude performance improvements for a wide range of applications.

Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge that conventional superscalar designs will not ...

CODACS (COnfigurable DAtaflow Computing System) project target is to realize a high performance reconfigurable computing system demonstrator able to directly execute in hardware dataflow graphs generated compiling programs written in CHIARA language. In ...

The advent of FPGAs and Intellectual Property core availability allow great freedom in the customization of platform processors for embedded systems. One of the new challenges that such technologies present is how to implement a high performance ...

With a focus on commodity PC systems, Beowulf clusters traditionally lack the cutting edge network architectures, memory subsystems, and processor technologies found in their more expensive supercomputer counterparts. What Beowulf clusters lack in ...

In this paper, we present CHIARA, the programminglanguage used to program CODACS (a general purposedataflow architecture exploiting FPGA technology), and describethe compiling strategies leading from CHIARA programsto the CODACS dataflow graphs. CHIARA ...

MuSiC, the highly-parallel Munich Simulation Computer, represents an approach for hardware-accelerated logic simulation by applying concepts developed for dataflow architectures to high-speed simulation of digital systems. This approach exploiting ...