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- research-articleDecember 2024
Fast and efficient hardware architecture of Chebyshev polynomials algorithm for resisting to side channel attacks: Fast and efficient hardware architecture...
The Journal of Supercomputing (JSCO), Volume 81, Issue 1https://doi.org/10.1007/s11227-024-06761-yAbstractThe field of embedded network security has seen increasing interest in developing lightweight and efficient chaotic map-based key exchange protocols. Due to their semi-group feature, Chebyshev polynomials are widely used in various protocols to ...
- research-articleSeptember 2024
Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization
- Prashanth Vijayaraghavan,
- Apoorva Nitsure,
- Charles Mackin,
- Luyao Shi,
- Stefano Ambrogio,
- Arvind Haran,
- Viresh Paruthi,
- Ali Elzein,
- Dan Coops,
- David Beymer,
- Tyler Baldwin,
- Ehsan Degan
MLCAD '24: Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CADArticle No.: 28, Pages 1–10https://doi.org/10.1145/3670474.3685966Large Language Models (LLMs) have become widely used across diverse NLP tasks and domains, demonstrating their adaptability and effectiveness. In the realm of Electronic Design Automation (EDA), LLMs show promise for tasks like Register-Transfer Level (...
- ArticleJuly 2024
Calculation of the Sigmoid Activation Function in FPGA Using Rational Fractions
Computational Science – ICCS 2024Pages 146–157https://doi.org/10.1007/978-3-031-63778-0_11AbstractIn this paper, we consider implementations of the sigmoid activation function for artificial neural network hardware systems. A rational fraction number system is proposed to calculate this function. This form of data representation offers several ...
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- research-articleJune 2024
GSGP-hardware: instantaneous symbolic regression with an FPGA implementation of geometric semantic genetic programming
Genetic Programming and Evolvable Machines (KLU-GENP), Volume 25, Issue 2https://doi.org/10.1007/s10710-024-09491-5AbstractGeometric Semantic Genetic Programming (GSGP) proposed an important enhancement to GP-based learning, incorporating search operators that operate directly on the semantics of the parents with bounded effects on the semantics of the offspring. This ...
- research-articleJuly 2024
FPGA realization of an image encryption system using the DCSK-CDMA technique
Integration, the VLSI Journal (INTG), Volume 96, Issue Chttps://doi.org/10.1016/j.vlsi.2024.102157AbstractThis paper describes a four-wing chaotic oscillator-based DCSK-CDMA modulation technique for image encryption and decryption. The system consists of a transmission module for the encrypted and modulated color matrices, and a reception module for ...
Highlights- Realization in FPGA of the DCSK-CDMA multi-user chaotic modulation and demodulation scheme. The architecture was designed using VHDL language with a word length of 40 bits for the manufacturer’s Xilinx Artix-7 AC701 card. The numerical ...
- research-articleJune 2024
HDLGen-ChatGPT Case Study: RISC-V Processor VHDL and Verilog Model - Testbench and EDA Project Generation
- Fearghal Morgan,
- John Patrick Byrne,
- Abishek Bupathi,
- Roshan George,
- Adnan Elahi,
- Frank Callaly,
- Seán Kelly,
- Declan O'Loughlin
RSP '23: Proceedings of the 34th International Workshop on Rapid System PrototypingArticle No.: 11, Pages 1–7https://doi.org/10.1145/3625223.3649280This paper presents the open source HDLGen-ChatGPT application, working in tandem with ChatGPT-3.5, the free online large language model (LLM) chat interface. The tools enable fast digital systems design and test specification capture, and automatic ...
- research-articleSeptember 2023
Study on the wireless sensor networks routing for Low-Power FPGA hardware in field applications
Computers and Electronics in Agriculture (COEA), Volume 212, Issue Chttps://doi.org/10.1016/j.compag.2023.108145Highlights- Wireless Sensor Networks (WSNs) are the preferred choice for the design and deployment of next-generation monitoring and control systems.
Very intelligent compact sensors with low-power and inexpensive solutions have been created because of the industrial revolution and subsequent advancements in electrical technology and wireless communications. Modern innovative ...
- research-articleAugust 2023
Experimental Study of Algorithms for Minimization of Binary Decision Diagrams Using Algebraic Representations of Cofactors
Programming and Computing Software (KLU-PACS), Volume 49, Issue 4Pages 268–285https://doi.org/10.1134/S0361768823040035AbstractBinary decision diagram (BDD) is used for technology-independent optimization, performed as the first stage in the synthesis of logic circuits in the design of application-specific integrated circuits (ASICs). BDD is an acyclic graph defining a ...
- research-articleAugust 2023
Hardware Implementation of Code Converters Designed to Reduce the Length of Binary Encoded Words
Programming and Computing Software (KLU-PACS), Volume 49, Issue 4Pages 247–267https://doi.org/10.1134/S0361768823040023AbstractThe problems of synthesis of combinational circuits of code converters designed to reduce the length of words from a given set of encoded binary words is considered. The encoding assumes that different binary words will be encoded by different ...
- extended-abstractJune 2023
Transpiling Nand2Tetris to VHDL for Teaching Digital Logic
ITiCSE 2023: Proceedings of the 2023 Conference on Innovation and Technology in Computer Science Education V. 2Pages 575–576https://doi.org/10.1145/3587103.3594161Nand2Tetris is a popular introduction to digital logic and computer organization that uses a simplified hardware description language (HDL) to program a hardware simulator. The stripped-down HDL allows students to focus on concepts over ceremony, but ...
- research-articleJune 2024
An Approach for a Project-Based Digital Logic Design Course Using an Innovative Simulator
WCAE '23: Proceedings of the Workshop on Computer Architecture EducationPages 48–54https://doi.org/10.1145/3605507.3610628A new tool called Visceral VCD was utilized to replace FPGA hardware during the pandemic. Its functionality was proven utilizing multiple projects in a digital logic course. The pedagogy of the assignments is discussed in detail, as well as how the use ...
- research-articleMay 2023
Hardware implementation and validation of the fast variable block size motion estimation architecture for HEVC Standard
Multimedia Tools and Applications (MTAA), Volume 82, Issue 30Pages 46331–46349https://doi.org/10.1007/s11042-023-15628-yAbstractHigh-Efficiency Video Coding (HEVC) has become popular according to its excellent coding performance, in particular in the case of high-resolution video applications. However, the significant gain in performance is accompanied by a higher encoding ...
- extended-abstractAugust 2023
QHDL: a Low-Level Circuit Description Language for Quantum Computing
CF '23: Proceedings of the 20th ACM International Conference on Computing FrontiersPages 201–204https://doi.org/10.1145/3587135.3592191This paper proposes a descriptive language called QHDL, akin to VHDL, to program gate-based quantum computing systems. Unlike other popular quantum programming languages, QHDL targets low-level quantum computing programming and aims to provide a common ...
- research-articleMarch 2023
PoCH: automatic HDL code generator tool for Polar channel coding decoders in multimedia communication systems
Multimedia Tools and Applications (MTAA), Volume 82, Issue 24Pages 36739–36768https://doi.org/10.1007/s11042-023-14507-wAbstractPolar codes are a class of block codes which are widely used in communication networks. Polar codes have been utilized in the fifth generation of enhanced mobile broadband systems (5G) due to their performance in error correction and also their ...
- ArticleDecember 2022
Automatic Generation of Verified Concurrent Hardware Using VHDL
Formal Methods: Foundations and ApplicationsPages 55–72https://doi.org/10.1007/978-3-031-22476-8_4AbstractThe complexity of development and analysis is inherent to systems in general, especially in concurrent systems. When working with critical systems this becomes much more evident, as inconsistencies are usually associated with a high cost. Thus, ...
- research-articleDecember 2022
A new hardware architecture of lightweight and efficient real-time video chaos-based encryption algorithm
Journal of Real-Time Image Processing (SPJRTIP), Volume 19, Issue 6Pages 1049–1062https://doi.org/10.1007/s11554-022-01244-wAbstractIn this paper, we propose a novel chaotic-based encryption scheme for securing real-time video data. The proposed encryption algorithm is based on the One-Time Pad (OTP) scheme and the unified Lorenz chaotic generator. The peculiarity of the ...
- research-articleNovember 2022
Hardware implementation of HEVC CABAC binarization/de-binarization
Journal of Visual Communication and Image Representation (JVCIR), Volume 89, Issue Chttps://doi.org/10.1016/j.jvcir.2022.103673Highlights- Hardware implementation of video compression and decompression processes.
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High efficiency video coding (HEVC) video codec applies different techniques in order to achieve high compression ratios and video quality that supports real-time applications. One of the critical techniques in HEVC is the Context ...
- ArticleJuly 2022
Implementing Synthetic Aperture Radar Backprojection in Chisel – A Field Report
Embedded Computer Systems: Architectures, Modeling, and SimulationPages 28–42https://doi.org/10.1007/978-3-031-15074-6_2AbstractChisel is an emerging hardware description language which is especially popular in the RISC-V community. In this report, we evaluate its application in the field of general digital hardware design. A dedicated hardware implementation of a ...