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- ArticleAugust 2019
SIRM: Shift Insensitive Racetrack Main Memory
Network and Parallel ComputingPages 355–360https://doi.org/10.1007/978-3-030-30709-7_33AbstractRacetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides ...
