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- research-articleSeptember 2024
NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance
ACM Transactions on Embedded Computing Systems (TECS), Volume 23, Issue 6Article No.: 96, Pages 1–30https://doi.org/10.1145/3677178Deep neural networks (DNNs) have been widely adopted, owing to break-through performance and high accuracy. DNNs exhibit varying memory behavior involving specific and recognizable memory access patterns and access intensity, depending on the selected ...
- research-articleDecember 2023
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 1Article No.: 19, Pages 1–35https://doi.org/10.1145/3630012Deep neural network (DNN) implementations are typically characterized by huge datasets and concurrent computation, resulting in a demand for high memory bandwidth due to intensive data movement between processors and off-chip memory. Performing DNN ...
- research-articleNovember 2020
eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex
- Dimitrios Stathis,
- Chirag Sudarshan,
- Yu Yang,
- Matthias Jung,
- Christian Weis,
- Ahmed Hemani,
- Anders Lansner,
- Norbert Wehn
Journal of Signal Processing Systems (JSPS), Volume 92, Issue 11Pages 1323–1343https://doi.org/10.1007/s11265-020-01562-xAbstractThe Artificial Neural Networks (ANNs), like CNN/DNN and LSTM, are not biologically plausible. Despite their initial success, they cannot attain the cognitive capabilities enabled by the dynamic hierarchical associative memory systems of biological ...
- research-articleSeptember 2019
3D photonics as enabling technology for deep 3D DRAM stacking
- Sebastian Werner,
- Pouya Fotouhi,
- Xian Xiao,
- Marjan Fariborz,
- S. J. Ben Yoo,
- George Michelogiannakis,
- Dilip Vasudevan
MEMSYS '19: Proceedings of the International Symposium on Memory SystemsPages 206–221https://doi.org/10.1145/3357526.33575593D stacking improves bandwidth, energy, and latency of DRAMs by exploiting shorter and more abundant wiring in three dimensions. While future stacks are predicted to provide tens of DRAM layers, TSV pitches are bound to stop decreasing due to physical ...
- research-articleJuly 2018
RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform
SAMOS '18: Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and SimulationPages 105–114https://doi.org/10.1145/3229631.3229650Artificial Neural Networks have been applied to many traditional machine learning applications in image and speech processing. More recently, ANNs have caught attention of the bioinformatics community for their ability to not only speed up by not having ...
- research-articleOctober 2017
Lightweight SIMT core designs for intelligent 3D stacked DRAM
MEMSYS '17: Proceedings of the International Symposium on Memory SystemsPages 49–59https://doi.org/10.1145/3132402.3132426In this work we present an analysis of the Harmonica stream multiprocessor, a light-weight, parameterized, open-source single-instruction-multiple-thread (SIMT) core designed for integration within 3D-stacked DRAM. We evaluate the range of Harmonica ...
- research-articleDecember 2015
Enabling portable energy efficiency with memory accelerated library
MICRO-48: Proceedings of the 48th International Symposium on MicroarchitecturePages 750–761https://doi.org/10.1145/2830772.2830788Over the last decade, the looming power wall has spurred a flurry of interest in developing heterogeneous systems with hardware accelerators. The questions, then, are what and how accelerators should be designed, and what software support is required. ...
- ArticleJuly 2009
Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking
ASAP '09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and ProcessorsPages 38–45https://doi.org/10.1109/ASAP.2009.11This work studies the potential of using emerging 3D integration to improve embedded VLIW computing system. We focus on the 3D integration of one VLIW processor die with multiple high-capacity DRAM dies. Our proposed memory architecture employs 3D ...