Article

Resynthesis of multi-level circuits under tight constraints using symbolic optimization

Authors:

Victor N. Kravets,

Karem A. SakallahAuthors Info & Claims

ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Pages 687 - 693

https://doi.org/10.1145/774572.774673

Published: 10 November 2002 Publication History

Abstract

We apply recently introduced constructive multi-level synthesis in the resynthesis loop targeting convergence of industrial designs. The incremental ability of the resynthesis approach allows more predictable circuit implementations while allowing their aggressive optimization. The approach is based on a very general symbolic decomposition template for logic synthesis that uses information-theoretical properties of a function to infer its decomposition patterns (rather than more conventional measures such as literal counts). Using this template the decomposition is done in a Boolean domain unrestricted by the representation of a function, enabling superior implementation choices driven by additional technological constraints. The symbolic optimization is applied in resynthesis of industrial circuits which have tight timing constraints yielding their much improved timing properties.

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Cited By

Chu ZSoeken MXia YDe Micheli GShin Y(2018)Functional decomposition using majorityProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201762(676-681)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201762
Puri RChoudhury MQian HZiegler MXie YKarnik TKhellah MMehra R(2014)Bridging high performance and low power in processor designProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2631642(183-188)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2631642
Elbayoumi MChoudhury MKravets VSullivan AHsiao MElnainay M(2014)TACUEProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593227(1-6)Online publication date: 1-Jun-2014
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Resynthesis of multi-level circuits under tight constraints using symbolic optimization

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cover image ACM Conferences

ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

November 2002

793 pages

ISBN:0780376072

DOI:10.1145/774572

General Chair:
Lawrence T. Pileggi
Carnegie Mellon Univ., Pittsburgh, PA
,
Program Chair:
Andreas Kuehlmann
Cadence Berkeley Labs., Berkeley, CA

Copyright © 2002 ACM.

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SIGDA: ACM Special Interest Group on Design Automation
IEEE Circuits & Systems Society
IEEE-CS\DATC: IEEE Computer Society

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Association for Computing Machinery

New York, NY, United States

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Published: 10 November 2002

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ICCAD02: 2002 IEEE / ACM International Conference on Computer Aided Design

November 10 - 14, 2002

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Chu ZSoeken MXia YDe Micheli GShin Y(2018)Functional decomposition using majorityProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201762(676-681)Online publication date: 22-Jan-2018
https://dl.acm.org/doi/10.5555/3201607.3201762
Puri RChoudhury MQian HZiegler MXie YKarnik TKhellah MMehra R(2014)Bridging high performance and low power in processor designProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2631642(183-188)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2631642
Elbayoumi MChoudhury MKravets VSullivan AHsiao MElnainay M(2014)TACUEProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593227(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593227
Plaza SMarkov IBertacco V(2008)Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic RestructuringIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2008.200615627:12(2107-2119)Online publication date: 1-Dec-2008
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Zhang JChrzanowska-Jeske MMishchenko ABurch JTang T(2005)Detecting support-reducing bound sets using two-cofactor symmetriesProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120846(266-271)Online publication date: 18-Jan-2005
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Zhang JChrzanowska-Jeske MMishchenko ABurch J(2005)Detecting support-reducing bound sets using two-cofactor symmetriesProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466171(266-271)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466171
Kravets VKudva PMalik SFix LKahng A(2004)Implicit enumeration of structural changes in circuit optimizationProceedings of the 41st annual Design Automation Conference10.1145/996566.996691(438-441)Online publication date: 7-Jun-2004
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Kung DMalik SFix LKahng A(2004)Timing closure for low-FO4 microprocessor designProceedings of the 41st annual Design Automation Conference10.1145/996566.996644(265-266)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996644
Mishchenko AWang XKam TGetreu IFix LLavagno L(2003)A new enhanced constructive decomposition and mapping algorithmProceedings of the 40th annual Design Automation Conference10.1145/775832.775871(143-148)Online publication date: 2-Jun-2003
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Kravets VKudva PSylvester DStroobandt DScheffer LZarkesh-Ha P(2003)Understanding metrics in logic synthesis for routability enhancementProceedings of the 2003 international workshop on System-level interconnect prediction10.1145/639929.639931(3-5)Online publication date: 5-Apr-2003
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