research-article

Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis

Authors:

Shahzad Ahmad Butt,

Luciano LavagnoAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 15, Issue 2

Article No.: 32, Pages 1 - 28

https://doi.org/10.1145/2871737

Published: 26 February 2016 Publication History

Abstract

Model-based hardware design allows one to map a single model to multiple hardware and/or software architectures, essentially eliminating one of the major limitations of manual coding in C or RTL. Model-based design for hardware implementation has traditionally offered a limited set of microarchitectures, which are typically suitable only for some application scenarios. In this article we illustrate how digital signal processing (DSP) algorithms can be modeled as flexible intellectual property blocks to be used within the popular Simulink model-based design environment. These blocks are written in C and are designed for both functional simulation and hardware implementation, including architectural design space exploration and hardware implementation through high-level synthesis. A key advantage of our modeling approach is that the very same bit-accurate model is used for simulation and high-level synthesis. To prove the feasibility of our proposed approach, we modeled a fast Fourier transform (FFT) algorithm and synthesized it for different DSP applications with very different performance and cost requirements. We also implemented a high-level-synthesis (HLS) intellectual property (IP) generator that can generate flexible FFT HLS-IP blocks that can be mapped to multiple micro-/macroarchitectures, to enable design space exploration as well as being used for functional simulation in the Simulink environment.

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Cited By

Streit FLetras MWildermann SHackenberg BFalk JBecher ATeich J(2018)Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/RECONFIG.2018.8641736(1-8)Online publication date: Dec-2018
https://doi.org/10.1109/RECONFIG.2018.8641736
Pagliari DCasu MCarloni L(2017)Accelerators for Breast Cancer DetectionACM Transactions on Embedded Computing Systems10.1145/298363016:3(1-25)Online publication date: 28-Mar-2017
https://dl.acm.org/doi/10.1145/2983630

Index Terms

Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 15, Issue 2

Special Issue on Innovative Design, Special Issue on MEMOCODE 2014 and Special Issue on M2M/IOT

May 2016

421 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2888407

Editor:
Sandeep K. Shukla
Indian Institute of Technology, India

Issue’s Table of Contents

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 26 February 2016

Accepted: 01 October 2015

Revised: 01 August 2015

Received: 01 March 2015

Published in TECS Volume 15, Issue 2

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Cited By

Streit FLetras MWildermann SHackenberg BFalk JBecher ATeich J(2018)Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/RECONFIG.2018.8641736(1-8)Online publication date: Dec-2018
https://doi.org/10.1109/RECONFIG.2018.8641736
Pagliari DCasu MCarloni L(2017)Accelerators for Breast Cancer DetectionACM Transactions on Embedded Computing Systems10.1145/298363016:3(1-25)Online publication date: 28-Mar-2017
https://dl.acm.org/doi/10.1145/2983630

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