research-article

Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems

Authors:

Gabriele Miorandi,

Davide BertozziAuthors Info & Claims

AISTECS '16: Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems

Article No.: 3, Pages 1 - 6

https://doi.org/10.1145/2857058.2857063

Published: 18 January 2016 Publication History

Abstract

Networks-on-chip (NoCs) are today at the core of multi- and many-core systems, acting as the system-level integration framework. In order to support scaling to future device generations, NoCs will struggle to deliver the required communication performance within tight power budgets. In this respect, evolutionary as well as revolutionary interconnect technologies are currently being considered. On one hand, clockless handshaking materializes GALS systems that completely remove the system clock while reducing idle power to only the leakage power. On the other hand, the technology platform could be changed, by replacing electrical wires with optical links and networks. This paper provides a comprehensive power analysis of the two technologies under test on a path-by-path basis, by comparing them with each other and with a baseline synchronous NoC. The outcome of this paper can support the selection of interconnect solutions for future manycore systems where power is the primary concern, as well as the runtime selection policy of routing paths in the context of hybrid interconnect fabrics.

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Cited By

(2018)Power-aware high level evaluation model of interconnect length of on-chip memory network topologyInternational Journal of Computational Science and Engineering10.5555/3292834.329284117:4(422-431)Online publication date: 20-Dec-2018
https://dl.acm.org/doi/10.5555/3292834.3292841

Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. Hardware

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AISTECS '16: Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems

January 2016

53 pages

ISBN:9781450340847

DOI:10.1145/2857058

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 18 January 2016

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AISTECS '16: 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems

January 18, 2016

Prague, Czech Republic

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Cited By

(2018)Power-aware high level evaluation model of interconnect length of on-chip memory network topologyInternational Journal of Computational Science and Engineering10.5555/3292834.329284117:4(422-431)Online publication date: 20-Dec-2018
https://dl.acm.org/doi/10.5555/3292834.3292841

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