Browse Theses

The high power consumption of a processor is becoming a critical problem for both battery-powered devices and high-performance computers. It reduces circuit reliability, complicates the cooling technology, shortens the battery lifetime, and increases the production and operation costs of a CPU. One effective technique, called dynamic voltage scaling (DVS), achieves CPU power reduction through lowering the CPU supply voltage and clock frequency at runtime. It is effective because the CPU power is proportional to the clock frequency and to the square of the supply voltage. However, the CPU power savings come at the cost of degraded performance due to the slower clock frequency. Furthermore, the longer the CPU runs, the more power other computer components (e.g., disk and screen) will consume; not to mention that a user may not be willing to sacrifice any performance. Therefore, DVS should only be applied when it will not noticeably affect performance. In this thesis I will present investigations on how compiler techniques can be used to minimize CPU power and energy consumption with almost no performance penalty. A compile-time DVS algorithm is proposed that uses a profile-driven program analysis to identify and slow down program regions whose performance bottleneck is not in the CPU. Simulations and physical measurements demonstrate the effectiveness of this strategy. Specifically, the total system power of a notebook computer can be reduced by up to 29% with a performance penalty of less than 5%. On average, the system power and energy savings are 10% and 11% at 2% of performance slowdown. To the best of my knowledge, this is one of the first works that demonstrate the effectiveness of a DVS algorithm via physical measurements. The thesis also discusses the impact of performance-oriented compiler optimizations on the proposed algorithm, the limit of energy savings that can be achieved through DVS, and how the DVS technique affects the design of a future computing system.