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Scheduling and allocation problems in high-level synthesis
  • Author:
  • Taewhan Kim
Publisher:
  • University of Illinois at Urbana-Champaign
  • Champaign, IL
  • United States
Order Number:UMI Order No. GAX94-11672
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Abstract

Various aspects of the two major tasks in high-level synthesis, scheduling and allocation, are studied in this thesis. Specifically, we study (1) the problem of scheduling dataflow graphs with conditional branches; (2) the problem of utilizing multi-port memories in data path synthesis; (3) the problem of integrating the scheduling and allocation steps; and (4) the problem of data path synthesis for testability.

Contributors
  • University of Illinois Urbana-Champaign

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