- Author:
- Cheng-Hsi Jesse Chen
This thesis studies the theoretical issues of floorplanning problems arising in the VLSI circuit layout design.
We present a parallel algorithm for finding the optimal implementations for the modules of a slicing floorplan that respects a given slicing tree. This algorithm runs in O(n) time and requires O(n) processors (i.e., we achieve optimal speedup). Moreover, our parallel algorithms do not need shared memory and can be implemented in a distributed system. We also present a more efficient parallel algorithm based on the EREW PRAM model. We show that in practice, the area optimization problem of slicing floorplans can be solved in O(log$\sp2$) time, using O(n) processors, on an EREW PRAM.
For non-slicing floorplans, we study the area optimization problem for spiral floorplans. In this thesis, we present an algorithm to find the optimal implementations of the modules of a spiral floorplan in O($k\sp2$logk) time, requires O($k\sp2$) space. The best known technique needs O($k\sp3$logk) time, O($k\sp3$) space, where k is the number of implementations of each module of a spiral floorplan. The improvement on both time and space are crucial when multi-level spiral floorplans are considered.
Our experimental data suggest that in most of the cases, the area optimization problem of multi-level spiral/slicing floorplans can be solved in O($n\sp2$logn) time and O($n\sp2$) space, where n is the number of modules of the floorplans.
In VLSI layout design, the routing phase immediately follows the phase of floorplanning. Slicing floorplans have only vertical and horizontal slices, each slice corresponds to a routing channel, and the channels are routed in the reverse order of slicing. The routing phase of a spiral floorplan is much more difficult than the routing phase of a slicing floorplan. In this thesis, we slicize a given spiral floorplan to become a slicing floorplan. Our experimental results indicate that in most cases, floorplans after slicizing produce better area than spiral floorplans. (Abstract shortened by UMI.)
Index Terms
- Area optimization of floorplan designs
Recommendations
An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs
In this article we propose an effective algorithm flow to handle modern large-scale mixed-size placement, both with and without geometry constraints. The basic idea is to use floorplanning to guide the placement of objects at the global level. The flow ...
Area reduction by deadspace utilization on interconnect optimized floorplan
Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of area, wirelength, and interconnect cost. These approaches can reduce the ...