Abstract
No abstract available.
Cited By
- Mukherjee N, Rajski J and Tyszer J (2001). Testing Schemes for FIR Filter Structures, IEEE Transactions on Computers, 50:7, (674-688), Online publication date: 1-Jul-2001.
- Carloni L and Sangiovanni-Vincentelli A Performance analysis and optimization of latency insensitive systems Proceedings of the 37th Annual Design Automation Conference, (361-367)
- Voyiatzis I, Paschalis A, Nikolos D and Halatsis C (1999). An Accumulator-Based BIST Approach for Two-Pattern Testing, Journal of Electronic Testing: Theory and Applications, 15:3, (267-278), Online publication date: 1-Dec-1999.
- Roh J and Abraham J Subband Filtering Scheme for Analog and Mixed-Signal Circuit Testing Proceedings of the 1999 IEEE International Test Conference
- Mukherjee N, Rajski J and Tyszer J Parameterizable Testing Scheme for FIR Filters Proceedings of the 1997 IEEE International Test Conference
- Gupta S, Rajski J and Tyszer J (1996). Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns, IEEE Transactions on Computers, 45:8, (939-949), Online publication date: 1-Aug-1996.
- Voyiatzis I, Paschalis A, Nikolos D and Halatsis C Accumulator-based BIST approach for stuck-open and delay fault testing Proceedings of the 1995 European conference on Design and Test
- Rajski J and Tyszer J (1993). Accumulator-Based Compaction of Test Responses, IEEE Transactions on Computers, 42:6, (643-650), Online publication date: 1-Jun-1993.
Index Terms
- Digital signal processing in VLSI