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Reviewer: Lanfranco Lopriore

MIPS is an application of the reduced instruction set computer (RISC) concept to the design of a microprocessor architecture. At present, this architecture is embodied by the R-Series (R2000, R3000, R6000, and the new R4000) processors. This book is a reference manual for the MIPS instruction set architecture and its implementation. Chapter 1 briefly discusses the salient characteristics of RISC architectures as opposed to complex instruction set computer (CISC) architectures. The issues considered include instruction pipelines, delayed load and delayed branch instructions, and instruction operation times. The importance of optimizing compiler techniques is stressed from the viewpoint of processor performance in terms of the program execution time. Chapter 2 introduces the MIPS processor architecture by reviewing a number of salient aspects of the R-Series processors. These include the instruction set, the pipeline structure, and the hierarchical organization of the memory system. The subsequent chapters treat these issues in depth. Chapter 3 deals specifically with the CPU instruction set. It illustrates the MIPS instruction formats and classifies the instructions into load and store, computational, jump and branch, and special instructions. The instructions in each class are briefly presented; the reader can refer to the 144-page Appendix A for a detailed description of the operation of each instruction. Chapter 4 describes the memory system architecture. The R-Series processors provide a memory management unit mapping a 2 32 -byte virtual address space into the physical memory space. Each processor features user and kernel operating modes. The kernel mode is reserved for the operating system. The R4000 processor provides a third mode, the supervisor mode, which is reserved for those components of the operating system that are not part of the kernel. The processor can access the entire virtual address space only when it operates in the kernel mode; in the supervisor and user modes, portions of the virtual space are not available. Virtual to physical address translation uses a translation lookaside buffer located either on-chip or (in the R6000) off-chip in a secondary cache. Chapter 5 deals with the cache memory system. This important component of the MIPS architecture is aimed at increasing the memory bandwidth to take full advantage of the high-performance RISC design. The MIPS processors use separate caches for instructions and data. Cache separation makes it possible to tailor the cache design to suit the different memory reference patterns, and introduces a form of address associativity. The instruction and data caches are on-chip in the R4000. This processor and the R6000 support an optional, off-chip secondary cache as well. Chapter 6 describes the types of exception that are handled by the MIPS processors and the actions performed as a consequence of the occurrence of an exception of each type. The architecture includes a floating-point unit (FPU), which is implemented directly on the R4000 chip and is embodied by the R2010, R3010, and R6000 floating-point accelerators for the other R-Series processors. The FPU operates as a coprocessor for the CPU. It conforms to ANSI/IEEE Standard 754-1985 in both single-precision (32-bit) and double-precision (64-bit) formats. Chapter 7 describes the FPU capabilities and programming model, paying special attention to the data representation and the FPU registers. The FPU features an instruction pipeline that parallels the CPU instruction pipeline. Chapter 8 illustrates this aspect of the FPU architecture and the FPU instruction set (Appendix B contains a detailed description of the operation of each FPU instruction). Finally, chapter 9 deals with the floating-point exceptions and exception trap processing. The book includes six appendices that detail several important aspects of the MIPS architecture. Appendices A and B are mentioned above. Appendix C gives a number of machine-language programming tips. Examples are the simulation of instructions and addressing modes that are not part of the MIPS instruction set architecture, and the detection of a carry, a borrow, or an overflow resulting from an arithmetic operation (the MIPS architecture does not include the carry and overflow status bits). Appendix D surveys the MIPS assembly language. Not all assembly language instructions have a direct machine language equivalent; the assembler synthesizes some assembly language instructions using sequences of machine instructions. Appendix E considers conformity of the MIPS floating-point coprocessor architecture with the requirements and recommendations of the IEEE standard. Finally, Appendix F contains a guide for the programmer to avoid those hazards connected with the instruction pipelining that, according to the MIPS architecture specifications, need not be detected and corrected by the hardware. Being a reference manual, the book concentrates on the description of the MIPS architecture. It places little emphasis on the motivations for the design choices that have been made among the various alternatives available within the RISC paradigm. The short analysis of the relevant issues in chapter 1 focuses on the differences between the RISC and CISC concepts. The discussion is often superficial; it will be of little help for readers not acquainted with the RISC concept, and almost useless for specialists. Unfortunately, no suggestions for further readings are given (see Patterson and Hennessy [1] and Tabak [2]). The exposition is often complicated by the fact that the different MIPS processors are presented in parallel within the chapters. A different organization of the book, separating the material relevant to each processor, might have made it easier to read. The salient advantage of intermixed presentation, that is, easier comparison of the various implementation choices, is almost never exploited. In fact, the book pays little attention to a comparative analysis of the performances of the different processors. Of course, limitations of this type are almost inevitable in a reference manual. Nonetheless, they reduce the range of the potential readers, essentially, to the computer professional involved in the development of a MIPS-based machine, and the specialist in RISC technology who wishes to obtain a deep insight into an important example of this technology.