Description

The artifact consists of four components: (1) source code for hardware loop identification over the benchmark suite of netlists; (2) source code for hardware loop rerolling over the benchmark suite; (3) scripts for comparing simulation times between decompiled HDL code with rerolled loops and the original netlist using Verilator; and (4) Yosys scripts for converting Verilog designs to netlists in BLIF. We provide instructions to reproduce the results reported in the evaluation.

Provenance

Source code provenance: University of California, Santa Barbara

Data set provenance: Some of the benchmarks in the evaluation are derived from work produced by the Bespoke Silicon Group (University of Washington)

License