research-article

Temperature reduction analysis in Sentry Tag cache systems

Authors:

Mostafa Farahani,

Amirali BaniasadiAuthors Info & Claims

MEDEA '09: Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture

Pages 22 - 27

https://doi.org/10.1145/1621960.1621964

Published: 13 September 2009 Publication History

Abstract

Power and temperature management continue to impose challenging issues in high-performance processor design. Processor power density is growing and has made building efficient cooling systems expensive. While Dynamic Thermal Management (DTM) techniques aim at reducing cooling systems cost, previously suggested low-temperature design could potentially provide further temperature reductions or help DTM operate more effectively.

Different processor components have different levels of impact on the overall temperature. Meantime, reducing the temperature of different processor components could result in both transient and steady temperature changes.

In this paper, we study the temperature impact of exploiting Sentry Tag caches on cache temperature. We show that by using the Sentry Tag it is possible to reduce cache temperature effectively. In addition, we show that using Sentry Tag can impact transient temperature behavior which in turn enhances DTM efficiency.

References

[1]

S. Borkar, "Design challenges of technology scaling", IEEE Micro, Vol. 19, Pages 23--29, Jul.--Aug 1999.

Digital Library

[2]

R. Mahajan, "Thermal management of CPUs: A perspective on trends, needs and opportunities", Keynote presentation at the 8th Int'l Workshop on Thermal Investigations of ICs and Systems, 2002.

[3]

S. Gunther, F. Binns, D. M. Carmean, and J. C. Hall, "Managing the impact of increasing microprocessor power consumption", Intel Technology Journal, Vol. 5, No. 1, 2001.

[4]

A. Abdollahi, F. Fallah, and M. Pedram, "Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 2, February 2004.

Digital Library

[5]

K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits", In Proceeding of the IEEE, Vol. 91, No. 2, February 2003.

[6]

K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, and D. Tarjana, "Temperature-Aware Microarchitecture: Modeling and Implementation", ACM Transactions on Architecture and Code Optimization, Vol. 1, No. 1, Pages 94--125, March 2004.

Digital Library

[7]

D. Brooks, and M. Martonosi, "Dynamic Thermal Management for High-Performance Microprocessors", In Proceedings of the 7th International Symposium on High-Performance Computer Architecture, Monterrey, Mexico, January 2001.

Digital Library

[8]

K. Skadron, T. Abdelzaher, M. R. Stan, "Control-Theoretic Techniques and Thermal-RC Modeling for Accurate and Localized Dynamic Thermal Management", In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture, Cambridge, Massachusetts, USA, Feb. 2--6, 2002.

Digital Library

[9]

Y. Chang, S. Ruan, and F. Lai, "Design and Analysis of Low-Power Cache Using Two-Level Filter Scheme", IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol. 11, No. 4, August 2003.

Digital Library

[10]

Y. Chang, S. Ruan, and F. Lai, "Sentry Tag. An Efficient Filter Scheme for Low Power Cache", In Proceedings of Seventh Asia-Pacific Computer Systems Architecture Conference, Melbourne, Australia, Conferences in Research and Practice in Information Technology, Vol. 6.

Digital Library

[11]

D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for architectural-level power analysis and optimizations", In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 83--94, June 2000.

Digital Library

[12]

SPEC CPU2000 Benchmarks, http://www.specbench.org.

[13]

W. Huang, K. Sankaranarayanan, R. J. Ribando, M. R. Stan, and K. Skadron, "An Improved HotSpot Block-Based Thermal Model with Granularity Considerations," In Proceeding of Workshop Duplicating, Deconstructing, and Debunking in conjunction with the Int'l Symposium Computer Architecture, June 2007.

[14]

C. Zhang, F. Vahid, J. Yang, and W. Najjar, "A Way-Halting Cache for Low-Energy High-Performance Systems", ACM Transactions on Architecture and Code Optimization, Vol. 2, No. 1, Pages 34--54, March 2005.

Digital Library

[15]

A. Hasegawa, I. Kawasaki, K. Yamada, S. Yoshioka, S. Kawasaki, P. Biswas, "SH3: high code density, low power", IEEE Micro, December 1995

Digital Library

Cited By

Chakraborty SKapoor H(2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
https://dl.acm.org/doi/10.1145/3339850
Chakraborty SKapoor H(2018)Analysing the Role of Last Level Caches in Controlling Chip TemperatureIEEE Transactions on Sustainable Computing10.1109/TSUSC.2018.28235423:4(289-305)Online publication date: 1-Oct-2018
https://doi.org/10.1109/TSUSC.2018.2823542
Chakraborty SKapoor H(2017)Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.3(75-80)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.3
Show More Cited By

Index Terms

Temperature reduction analysis in Sentry Tag cache systems
1. Computer systems organization
  1. Architectures

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cover image ACM Other conferences

MEDEA '09: Proceedings of the 10th workshop on MEmory performance: DEaling with Applications, systems and architecture

September 2009

48 pages

ISBN:9781605588308

DOI:10.1145/1621960

Conference Chairs:
Sandro Bartolini
Università di Siena
,
Pierfrancesco Foglia
Università di Pisa
,
Roberto Giorgi
Università di Siena
,
Cosimo Antonio Prete
Università di Pisa

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 13 September 2009

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MEDEA '09

MEDEA '09: The 2009 workshop on MEmory performance: DEaling with Applications, systems and architectures

September 13, 2009

North Carolina, Raleigh, USA

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Overall Acceptance Rate 6 of 9 submissions, 67%

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Cited By

Chakraborty SKapoor H(2019)Exploring the Role of Large Centralised Caches in Thermal Efficient Chip DesignACM Transactions on Design Automation of Electronic Systems10.1145/333985024:5(1-28)Online publication date: 28-Jun-2019
https://dl.acm.org/doi/10.1145/3339850
Chakraborty SKapoor H(2018)Analysing the Role of Last Level Caches in Controlling Chip TemperatureIEEE Transactions on Sustainable Computing10.1109/TSUSC.2018.28235423:4(289-305)Online publication date: 1-Oct-2018
https://doi.org/10.1109/TSUSC.2018.2823542
Chakraborty SKapoor H(2017)Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.3(75-80)Online publication date: Jan-2017
https://doi.org/10.1109/VLSID.2017.3
Taherian MBaniasadi ANoori H(2011)Instruction and data cache peak temperature reduction using cache access balancing in embedded processorsProceedings of the 2011 9th IEEE/ACS International Conference on Computer Systems and Applications10.1109/AICCSA.2011.6126591(285-286)Online publication date: 27-Dec-2011
https://dl.acm.org/doi/10.1109/AICCSA.2011.6126591

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