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- research-articleSeptember 2024
DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 5Article No.: 80, Pages 1–22https://doi.org/10.1145/3663476High-quality passive devices are becoming increasingly important for the development of mobile devices and telecommunications, but obtaining such devices through simulation and analysis of electromagnetic (EM) behavior is time-consuming. To address this ...
- research-articleAugust 2024
Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 5Article No.: 73, Pages 1–23https://doi.org/10.1145/3659950Transistor aging leads to the deterioration of analog circuit performance over time. The worst aging degradation is used to evaluate the circuit reliability. It is extremely expensive to obtain it since several circuit stimuli need to be simulated. The ...
- research-articleJuly 2024
CABC: A Cross-Domain Authentication Method Combining Blockchain with Certificateless Signature for IIoT
Future Generation Computer Systems (FGCS), Volume 158, Issue CPages 516–529https://doi.org/10.1016/j.future.2024.04.042Highlights- Addressing the problem that the certificateless signature algorithm has linearization loopholes and is vulnerable to forgery attacks, an improved certificateless signature scheme with elliptic curve cryptography is proposed, which is not ...
Device management in the Industrial Internet of Things (IIoT) is complex, especially in a cross-domain context. Trust identity authentication between cross-domain devices is required when devices work together. Existing identity authentication ...
- research-articleJune 2024
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024Pages 440–445https://doi.org/10.1145/3649476.3658754To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulations, leading to difficulty in converging design parameters and excessive ...
- research-articleMay 2024
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 3Article No.: 56, Pages 1–17https://doi.org/10.1145/3653453In this article, we focus on chip floorplanning, which aims to determine the location and orientation of circuit macros simultaneously, so the chip area and wirelength are minimized. As the highest level of abstraction in hierarchical physical design, ...
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- research-articleMay 2024
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 29, Issue 3Article No.: 53, Pages 1–25https://doi.org/10.1145/3652855In the digital era, the prevalence of low-quality images contrasts with the widespread use of high-definition displays, primarily due to low-resolution cameras and compression technologies. Image super-resolution (SR) techniques, particularly those ...
- research-articleMarch 2024
Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 9Pages 2755–2768https://doi.org/10.1109/TCAD.2024.3379016As the transistor technology nodes shrink into the nano-scales, timing guardbands caused by aging effects and process variations continue to increase. Approximate computing can eliminate aging-and-variation-induced timing guardbands without sacrificing ...
- research-articleMarch 2024
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 9Pages 2674–2686https://doi.org/10.1109/TCAD.2024.3378600Optical proximity correction (OPC) is a widely used technique to enhance the printability of designs in various foundaries. Recently, there has been a growing interest in using rigorous numerical optimization and machine learning to improve the robustness ...
- invited-talkMarch 2024
Large Language Models for EDA: Future or Mirage?
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPages 65–66https://doi.org/10.1145/3626184.3639700In this paper, we explore the burgeoning intersection of Large Language Models (LLMs) and Electronic Design Automation (EDA). We critically assess whether LLMs represent a transformative future for EDA or merely a fleeting mirage. By analyzing current ...
- research-articleMarch 2024
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPages 75–82https://doi.org/10.1145/3626184.3633322Face-to-face (F2F) stacked 3D IC is a promising alternative for scaling beyond Moore's Law. In F2F 3D ICs, dies are connected through bonding terminals whose positions can significantly impact routing performance. Further, there exists resource ...
- research-articleMarch 2024
IncreMacro: Incremental Macro Placement Refinement
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPages 169–176https://doi.org/10.1145/3626184.3633321This paper proposes IncreMacro, a novel approach for macro placement refinement in the context of integrated circuit (IC) design. The suggested approach iteratively and incrementally optimizes the placement of macros in order to enhance IC layout ...
- research-articleMarch 2024
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPages 161–168https://doi.org/10.1145/3626184.3633320A circuit design incorporating non-integer multi-height (NIMH) cells, such as a combination of 8-track and 12-track cells, offers increased flexibility in optimizing area, timing, and power simultaneously. The conventional approach for placing NIMH cells ...
- research-articleMarch 2024
FuILT: Full Chip ILT System With Boundary Healing
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPages 13–20https://doi.org/10.1145/3626184.3633315Mask optimization in lithography is becoming increasingly impor- tant as the technology node size shrinks down. Inverse Lithography Technology (ILT) is one of the most performant and robust solutions widely used in the industry, yet it still suffers from ...
- research-articleMarch 2024
FGDB‐MLPP: A fine‐grained data‐sharing scheme with blockchain based on multi‐level privacy protection
IET Communications (CMU2), Volume 18, Issue 4Pages 309–321https://doi.org/10.1049/cmu2.12737AbstractIn the era of 5G, billions of terminal devices achieve global interconnection and intercommunication, which leads to the generation of massive data. However, the existing cloud‐based data‐sharing mechanism faces challenges such as sensitive ...
(1) A blockchain‐based efficient data‐sharing scheme is proposed, which employs the ciphertext policy attribute‐based encryption algorithm to enable fine‐grained sharing of data resources.
(2) An anonymous identity authentication method based on ring ...
- research-articleFebruary 2024
SDAC-BBPP: A Secure Dynamic Access Control Scheme With Blockchain-Based Privacy Protection for IIoT
IEEE Transactions on Network and Service Management (ITNSM), Volume 21, Issue 3Pages 3179–3193https://doi.org/10.1109/TNSM.2024.3371521Industrial big data has experienced from data silos due to its high potential value and strong security requirements, making it difficult to share securely across domains. Blockchain-based solutions allow nodes to establish access control to trusted data ...
- research-articleFebruary 2024
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCADICS), Volume 43, Issue 7Pages 2140–2150https://doi.org/10.1109/TCAD.2024.3361400Source mask optimization (SMO) is vital for mitigating lithography imaging distortions caused by shrinking critical dimensions in integrated circuit fabrication. However, the computational intensity of SMO, involving multiple integrals in Abbe’s ...
- research-articleApril 2024
iEDA: An Open-Source Infrastructure of EDA
- Xingquan Li,
- Zengrong Huang,
- Simin Tao,
- Zhipeng Huang,
- Chunan Zhuang,
- Hao Wang,
- Yifan Li,
- Yihang Qiu,
- Guojie Luo,
- Huawei Li,
- Haihua Shen,
- Mingyu Chen,
- Dongbo Bu,
- Wenxing Zhu,
- Ye Cai,
- Xiaoming Xiong,
- Ying Jiang,
- Yi Heng,
- Peng Zhang,
- Bei Yu,
- Biwei Xie,
- Yungang Bao
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 77–82https://doi.org/10.1109/ASP-DAC58780.2024.10473983By leveraging the power of open-source software, the EDA tool offers a cost-effective and flexible solution for designers, researchers, and hobbyists alike. Open-source EDA promotes collaboration, innovation, and knowledge sharing within the EDA ...
- research-articleApril 2024
V-GR: 3D Global Routing with via Minimization and Multi-Strategy Rip-Up and Rerouting
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 963–968https://doi.org/10.1109/ASP-DAC58780.2024.10473939In VLSI, a large number of vias may reduce manufacturability, degrade circuit performance, and increase layout area required for interconnection. In this paper, we propose a 3D global router V-GR, which considers minimizing the number of vias. V-GR uses ...
- research-articleApril 2024
iPD: An Open-Source Intelligent Physical Design Toolchain
- Xingquan Li,
- Simin Tao,
- Shijian Chen,
- Zhisheng Zeng,
- Zhipeng Huang,
- Hongxi Wu,
- Weiguo Li,
- Zengrong Huang,
- Liwei Ni,
- Xueyan Zhao,
- He Liu,
- Shuaiying Long,
- Ruizhi Liu,
- Xiaoze Lin,
- Bo Yang,
- Fuxing Huang,
- Zonglin Yang,
- Yihang Qiu,
- Zheqing Shao,
- Jikang Liu,
- Yuyao Liang,
- Biwei Xie,
- Yungang Bao,
- Bei Yu
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 83–88https://doi.org/10.1109/ASP-DAC58780.2024.10473932Open-source electronic design automation (EDA) shows promising potential in unleashing EDA innovation and lowering the cost of chip design. The open-source EDA toolchain is a comprehensive set of software tools designed to facilitate the design, analysis,...
- research-articleApril 2024
LSTP : A Logic Synthesis Timing Predictor
ASPDAC '24: Proceedings of the 29th Asia and South Pacific Design Automation ConferencePages 728–733https://doi.org/10.1109/ASP-DAC58780.2024.10473925The ever-growing complexity of modern VLSI circuits brings about a substantial increase in the design cycle. As for logic synthesis, how to efficiently obtain physical characteristics of a design for subsequent design space exploration emerges as a ...