• Muchherla K, Chen P, Ma D and Wang J. (2008). A noniterative equivalent waveform model for timing analysis in presence of crosstalk. ACM Transactions on Design Automation of Electronic Systems. 13:2. (1-21). Online publication date: 2-Apr-2008.

    https://doi.org/10.1145/1344418.1344421

  • Roy A, Mahmoud N and Chowdhury M. Effects of coupling capacitance and inductance on delay uncertainty and clock skew. Proceedings of the 44th annual Design Automation Conference. (184-187).

    https://doi.org/10.1145/1278480.1278525

  • Chen R and Zhou H. Timing macro-modeling of IP blocks with crosstalk. Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design. (155-159).

    https://doi.org/10.1109/ICCAD.2004.1382563

  • Kim K, Jung S, Kim T, Saxena P, Liu C and Kang S. (2003). Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11:5. (879-887). Online publication date: 1-Oct-2003.

    https://doi.org/10.1109/TVLSI.2003.817111

  • Kim K, Jung S, Narayanan U, Liu C and Kang S. (2003). Noise-aware interconnect power optimization in domino logic synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 11:1. (79-89). Online publication date: 1-Feb-2003.

    https://doi.org/10.1109/TVLSI.2002.801630

  • Batterywala S and Shenoy N. A Method to Estimate Slew and Delay in Coupled Digital Circuits. Proceedings of the 16th International Conference on VLSI Design.

    /doi/10.5555/832285.835589

  • Chen P, Kukimoto Y and Keutzer K. Refining switching window by time slots for crosstalk noise calculation. Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design. (583-586).

    https://doi.org/10.1145/774572.774658

  • Chen P, Kukimoto Y, Teng C and Keutzer K. On convergence of switching windows computation in presence of crosstalk noise. Proceedings of the 2002 international symposium on Physical design. (84-89).

    https://doi.org/10.1145/505388.505410

  • Agarwal K, Cao Y, Sato T, Sylvester D and Hu C. Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. Proceedings of the 2002 Asia and South Pacific Design Automation Conference.

    /doi/10.5555/832284.835482

  • Kim K, Jung S, Saxena P, Liu C and Kang S. Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. Proceedings of the 38th annual Design Automation Conference. (732-737).

    https://doi.org/10.1145/378239.379056

  • Zhou H, Shenoy N and Nicholls W. Timing analysis with crosstalk as fixpoints on complete lattice. Proceedings of the 38th annual Design Automation Conference. (714-719).

    https://doi.org/10.1145/378239.379053

  • A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. Proceedings of the 2nd International Symposium on Quality Electronic Design.

    /doi/10.5555/558593.850188

  • Wilton S. A crosstalk-aware timing-driven router for FPGAs. Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays. (21-28).

    https://doi.org/10.1145/360276.360292

  • Chen P, Kirkpatrick D and Keutzer K. Switching window computation for static timing analysis in presence of crosstalk noise. Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design. (331-337).

    /doi/10.5555/602902.602978

  • Chen P, Kirkpatrick D and Keutzer K. Miller factor for gate-level coupling delay calculation. Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design. (68-75).

    /doi/10.5555/602902.602919