• Bruchertseifer J, Fernau H, Holzer M and Sempere J. (2021). Synchronizing series-parallel deterministic finite automata with loops and related problems. RAIRO - Theoretical Informatics and Applications. 10.1051/ita/2021005. 55. (7).

    https://www.rairo-ita.org/10.1051/ita/2021005

  • Szykuła M. (2015). Checking Whether an Automaton Is Monotonic Is NP-complete. Implementation and Application of Automata. 10.1007/978-3-319-22360-5_23. (279-291).

    https://link.springer.com/10.1007/978-3-319-22360-5_23

  • Pocci M, Demongodin I, Giambiasi N and Giua A. Synchronizing sequences on not strongly connected Petri nets (Work-in-Progress). Proceedings of the 2011 Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium. (45-50).

    /doi/10.5555/2048476.2048481

  • Volkov M. Synchronizing Automata and the Černý Conjecture. Language and Automata Theory and Applications. (11-27).

    https://doi.org/10.1007/978-3-540-88282-4_4

  • Pomeranz I and Reddy S. (2006). On synchronizable circuits and their synchronizing sequences. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 19:9. (1086-1092). Online publication date: 1-Nov-2006.

    https://doi.org/10.1109/43.863649

  • Trahtman A. An efficient algorithm finds noticeable trends and examples concerning the Černy conjecture. Proceedings of the 31st international conference on Mathematical Foundations of Computer Science. (789-800).

    https://doi.org/10.1007/11821069_68

  • Bertoli P and Cimatti A. Improving heuristics for planning as search in belief space. Proceedings of the Sixth International Conference on Artificial Intelligence Planning Systems. (143-152).

    /doi/10.5555/3036884.3036905

  • Corno F, Prinetto P, Rebaudengo M, Reorda M and Squillero G. (2002). Initializability analysis of synchronous sequential circuits. ACM Transactions on Design Automation of Electronic Systems. 7:2. (249-264). Online publication date: 1-Apr-2002.

    https://doi.org/10.1145/544536.544538

  • Cimatti A, Roveri M and Bertoli P. (2001). Searching Powerset Automata by Combining Explicit-State and Symbolic Model Checking. Tools and Algorithms for the Construction and Analysis of Systems. 10.1007/3-540-45319-9_22. (313-327).

    http://link.springer.com/10.1007/3-540-45319-9_22

  • Singh M and Nowick S. (2000). Synthesis for logical initializability of synchronous finite-state machines. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8:5. (542-557). Online publication date: 1-Oct-2000.

    https://doi.org/10.1109/92.894160

  • Wehbeh J and Saab D. (1998). Initialization of Sequential Circuits and its Application to ATPG. Journal of Electronic Testing: Theory and Applications. 13:3. (259-271). Online publication date: 1-Dec-1998.

    https://doi.org/10.1023/A:1008333803059

  • Pomeranz I and Reddy S. On synchronizing sequences and test sequence partitioning 16th IEEE VLSI Test Symposium. 10.1109/VTEST.1998.670864. 0-8186-8436-4. (158-167).

    http://ieeexplore.ieee.org/document/670864/

  • Singh M and Nowick S. Synthesis for Logical Initializability of Synchronous Finite State Machines. Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications.

    /doi/10.5555/523974.834852

  • Singh M and Nowick S. Synthesis for logical initializability of synchronous finite state machines Tenth International Conference on VLSI Design. 10.1109/ICVD.1997.567964. 0-8186-7755-4. (76-80).

    http://ieeexplore.ieee.org/document/567964/

  • Corno F, Prinetto P, Rebaudengo M, Sonza Reorda M and Squillero G. A new approach for initialization sequences computation for synchronous sequential circuits International Conference on Computer Design VLSI in Computers and Processors. 10.1109/ICCD.1997.628898. 0-8186-8206-X. (381-386).

    http://ieeexplore.ieee.org/document/628898/

  • Corno F, Prinetto P, Rebaudengo M, Reorda M and Squillero G. A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits Sixth Asian Test Symposium (ATS'97). 10.1109/ATS.1997.643917. 0-8186-8209-4. (56-61).

    http://ieeexplore.ieee.org/document/643917/

  • Wehbeh J and Saab D. Initialization of sequential circuits and its application to ATPG 14th VLSI Test Symposium. 10.1109/VTEST.1996.510864. 0-8186-7304-4. (246-251).

    http://ieeexplore.ieee.org/document/510864/

  • Lu Y and Pomeranz I. Synchronization of large sequential circuits by partial reset 14th VLSI Test Symposium. 10.1109/VTEST.1996.510841. 0-8186-7304-4. (93-98).

    http://ieeexplore.ieee.org/document/510841/

  • Saluja E. Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan. Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing.

    /doi/10.5555/874064.875658

  • Ning Jiang , Chou R and Saluja E. Synthesizing finite state machines for minimum length synchronizing sequence using partial scan Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers. 10.1109/FTCS.1995.466980. 0-8186-7079-7. (41-49).

    http://ieeexplore.ieee.org/document/466980/

  • Wahbeh J and Saab D. On the initialization of sequential circuits. Proceedings of the 1994 international conference on Test. (233-239).

    /doi/10.5555/1895949.1895985

  • Wahbeh J and Saab D. On the initialization of sequential circuits International Test Conference. 10.1109/TEST.1994.527954. 0-7803-2102-2. (233-239).

    http://ieeexplore.ieee.org/document/527954/