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M. Jagadesh Kumar

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2020 – today

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2020
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Vivek Asthana, M. Jagadesh Kumar, Ayush Kulshrestha, Munish Kumar, Saikat Kumar Banik, Shruti Aggarwal:
0.25pA/Bit Ultra-Low-Leakage 6T Single-Port SRAM on 22nm Bulk Process for IoT Applications. ISCAS 2020: 1-5

2000 – 2009

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2006
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M. Jagadesh Kumar, Ali A. Orouji:
Phase Change Memory Faults. VLSI Design 2006: 108-112
2004
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Anurag Chaudhry, M. Jagadesh Kumar:
Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies. VLSI Design 2004: 662-665

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